Hardware Description Languages (HDLs), such as the Very high-speed integrated circuit Hardware Description Language (VHDL) or VERILOG are text-based approaches to digital logic design through behavioral and/or structural description of design elements. HDL can be used to design: (1) a programmable logic device (PLD), such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD); (2) a mask programmable device, such as a hardwired programmable gate array (PGA), application-specific standard product (ASSP) or application specific integrated circuit (ASIC); (3) a system formed from selected electronic hardware components; or (4) any other electronic device. The HDL-based approach to design requires the user to describe the behavior of a system, which can then be simulated to determine whether the design will function as desired. The design is then synthesized to create a logical network list (“netlist”) that can be implemented within a particular device.
Many tools exist that allow electronic designs of integrated circuits (ICs) to be assembled, simulated, debugged, and translated into hardware. In general, an IC modeling system allows an IC design to be described and simulated with a HDL-level abstraction. For example, a designer produces an electronic representation of the IC design using a modeling system by connecting and arranging schematic representations of circuit elements on a computer display, then uses the modeling system to translate the electronic IC design to a lower level HDL description for simulation or realization in hardware.
A logic simulator is a software tool capable for performing functional and timing simulation of an HDL circuit design. Logic simulators perform the process of elaboration, in which a circuit description in HDL takes effect inside the logic simulator. The elaboration process constructs each logic component, assigns initial values to generics/parameters/signals, and establishes connections between logic components.
A circuit design often consists of many different components, possibly written in different HDLs. For example, a circuit design may have some components described using VHDL and other components described using VERILOG. Conventional logic simulators exist for simulating pure VHDL designs or pure VERILOG designs. Since circuit designs may be described using multiple HDLs, there exists a need for a logic simulator which simulates a mixed HDL description. One of the main challenges of VHDL/VERILOG mixed-language simulation is that VHDL and VERILOG have different elaboration semantics (i.e., they require different object construction, initial value calculation, and assignment order). Accordingly, there exists a need in the art for an improved method and apparatus that processes a mixed-language circuit description for logic simulation.